The present invention relates to a semiconductor device and a control method of its internal circuit. In particular, the present invention relates to a semiconductor device including a power-supply circuit that converts the voltage of an externally-supplied electrical power into a different voltage inside the semiconductor device and supplies the converted voltage to internal circuits, and a control method of its internal circuit.
In semiconductor devices, the cost reduction has been achieved by increasing the packaging density and thereby reducing the chip size. Therefore, the miniaturization of the transistors, which constitute memory elements and logic circuits constituting a semiconductor device, has been pursued. Further, as the memory elements and the transistors are miniaturized, it is necessary to lower the internal power-supply voltage applied to these devices in terms of the reliability. However, in order to maintain the compatibility of semiconductor devices with the existing products in the product specifications, there are cases where the power-supply voltage supplied to a semiconductor device needs to be maintained at the conventional voltage, which is higher than the internal power-supply voltage of that semiconductor device.
For example, there is a case where although the specifications of a semiconductor device specify that 1.8 V is to be supplied as the external power-supply voltage, the internal power-supply voltage applicable to the memory elements and the transistors is set to 1.2 V in terms of the reliability. In the case like this, the external power-supply voltage of 1.8 V is lowered to 1.2V by using a voltage-lowering circuit provided within the semiconductor device to generate the internal power-supply voltage, and the generated internal power-supply voltage is supplied to the internal circuits such as an SRAM memory, a DRAM memory, and a logic circuit.
In semiconductor devices like this in which a DC (Direct-Current) voltage conversion circuit such as a voltage-lowering circuit is provided, there are cases where an internal circuit(s), which receives the internal power-supply voltage from the DC voltage conversion circuit, switches its operation state between an operating state and a suspended state. In such cases, a voltage drop occurs in the internal power-supply voltage when the internal circuit switches between an operating state and a suspended state. This voltage drop occurs because the current consumption of the internal circuit rises when the internal circuit changes from a suspended state to an operating state and there is a certain delay between when the current consumption rises and when the DC voltage conversion circuit detects the rise in the current consumption and increases its current supply capability. In the following explanation, the period between when the internal power-supply voltage VDL drops and when the DC voltage conversion circuit starts the current supply is referred to as “response delay period”. Accordingly, Japanese Unexamined Patent Application Publication No. 2001-127254 discloses a technique to suppress the fluctuations in the internal power-supply voltage like this.
FIG. 17 shows a schematic diagram of a block layout of a semiconductor device 100 disclosed in Japanese Unexamined Patent Application Publication No. 2001-127254. The semiconductor device 100 shown in FIG. 17 includes a DRAM macro (e.g., memory arrays MA0 and MA1), power-supply control circuits 110a, 110b and 110c, active unit groups 111a and 111b, decoupling capacitances 112a and 112b. In this example, each of the memory arrays MA0 and MA1 has a storage capacity of 16 Mbits at the maximum. Further, the active unit group 111a and the decoupling capacitance 112a are provided for the memory array MA0. The active unit group 111b and the decoupling capacitance 112b are provided for the memory array MA1. The power-supply control circuit 110c is disposed between the power-supply control circuits 110a and 110b. 
The power-supply control circuit 110a includes a reference voltage generation circuit that generates a reference voltage VrefS used to generate an array voltage VCCS. The power-supply control circuit 110b includes a circuit that generates a frequency-division clock signal PCLK used to generates a raised voltage VPP. The power-supply control circuit 110c includes a control circuit that generates an array activation signal ACT, an intermediate voltage generation circuit that generates intermediate voltages VBL and VCP, and a standby voltage-lowering circuit. Further, each of the active unit groups 111a and 111b includes DC voltage conversion circuits that generate predetermined voltages (VPP and VCCS) according to the reference voltage VrefS and the control signal ACT. More specifically, each of the active unit groups 111a and 111b includes an active unit AUP that constitutes a Vpp pump, and an active unit AUV that constitutes an active voltage-lowering circuit. The number of the active units AUV and AUP provided in each of these active unit groups 111a and 111b is determined as appropriate according to the storage capacity of the memory arrays MA0 and MA1 and the operating conditions. The decoupling capacitance 112a is disposed between the active unit group 111a and the memory array MA0. The decoupling capacitance 112b is disposed between the active unit group 111b and the memory array MA1.
As described above, in the semiconductor device 100, the decoupling capacitances 112a and 112b are provided between the active unit groups 111a and 111b, which supply the internal power-supply voltage VCCS and the like to the memory arrays MA0 and MA1, and the memory arrays MA0 and MA1. In the semiconductor device 100, the current that is consumed during the response delay period of the active units AUP and AUV of the active unit groups 111a and 111b is covered by the electrical charge accumulated in the decoupling capacitances. In this way, the semiconductor device 100 suppresses the voltage fluctuations in the internal power-supply voltage VCCS and the like during the response delay period.